Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 807 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 18-83
External Bus Interface Unit
When the external buffer timing (
EBUFE = 1
in the SDRAM Memory
Global Control register) and/or CAS latency of 3 (
CL = 11
in the SDRAM
Memory Global Control register) is used, all accesses take one extra cycle
for each feature selected. Accesses that hit in the Read Buffer follow these
rules:
If either
EBUFE = 1
or
CL = 11
:
• For N = 8 to 6, N half word hit: 8 words/8 cycles
• For N = 5 to 0, N half word hit: 8 words/(14 – N) cycles
If both
EBUFE = 1
and
CL = 11
:
• For N = 8 to 7, N half word hit: 8 words/8 cycles
• For N = 6 to 0, N half word hit: 8 words/(15 – N) cycles
Table 18-20 lists the data throughput rates for the core or DMA
read/write accesses to 16-bit wide SDRAM. For this example, assume all
cycles are
SCLK
cycles and the following
SCLK
frequency and SDRAM
parameters are used:
•
SCLK
frequency = 133 MHz
• CAS latency = 2 cycles (
CL = 2
)
• No SDRAM buffering (
EBUFE = 0
)
• RAS precharge (t
RP
) = 2 cycles (
TRP = 2
)
• RAS to CAS delay (t
RCD
) = 2 cycles (
TRCD = 2
)
• Active command time (t
RAS
) = 5 cycles (
TRAS = 5
)