Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Core Overview
7-4 ADSP-BF535 Blackfin Processor Hardware Reference
The off-core system is master to a dedicated L1 interface (System L1 bus).
This bus provides direct memory access to L1 memory configured as
SRAM, except for the Scratchpad SRAM. L1 memory configured as cache
is not accessible by the off-core system.
The Core I bus, the Core D0 bus, the Core D1 bus, and the System L1
bus run at the full core frequency, have data paths up to 64 bits, and sup-
port burst transfers. All four ports have 32-bit address buses. The Core D0
Figure 7-2. Blackfin Processor Core Block Diagram
INT
ACK
TIMER
EVENT
CONTROLLER
DEBUG AND JTAG INTERFACE
JTAG
DSP I D
(8 BITS)
SRAM BASE
ADDRESS
SYSTEM CLOCK
AND POWER
MANAG EMENT
POWER AND
CLOCK
CONTROLLER
PERFORMANCE
MONITO R
MEMORY
MANAGEMENT
UNIT
L1 DATA MEMORY
L1 INSTRUCTIO N MEMO RY
L
D
0
L
D
1
S
D
D
A
0
D
A
1
IA
B
ID
B
4K SRAM
DCACHE/SRAM
I CACHE/SRAM
SYSTEM BUS I NTERFACE UNIT (SBIU)
CORE
CONTROL
PROCESSOR
CORE D0 BUS CORE D1 BUS CORE I BUS
32 32 32 32 32 64 32
SYSL1 BUS
RESET
VECTOR