Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 10-7
SPI Compatible Port Controllers
SPI Registers
The SPI peripheral on the ADSP-BF535 processor includes a number of
user-accessible registers. Some of these registers are also accessible through
the DMA bus. Four registers contain control and status information:
SPIx_BAUD
,
SPIx_CTL
,
SPIx_FLG
, and
SPIx_ST
. Two registers are used for
buffering receive and transmit data:
SPIx_RDBR
and
SPIx_TDBR
. Eight reg-
isters are related to DMA functionality. The shift register,
SFDR
, is internal
to the SPI module and is not directly accessible.
See “Error Signals and Flags” on page 10-35 for more information about
how the bits in these registers are used to signal errors and other condi-
tions. See
“Register Functions” on page 10-26 for more information about
SPI register and bit functions.
Non-DMA Registers
The following sections describes the SPI non-DMA registers.
SPIx Baud Rate Register (SPIx_BAUD)
The SPIx Baud Rate register (
SPIx_BAUD
) is used to set the bit transfer rate
for a master device. When configured as a slave, the value written to this
register is ignored. The serial clock frequency is determined by this
formula:
•
SCKx
frequency = (System clock frequency)/(2

SPIx_BAUD
)
Writing a value of 0 or 1 to the register disables the serial clock. There-
fore, the maximum serial clock rate is one-fourth the system clock rate.