Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 9-31
Direct Memory Access
Memory DMA (MemDMA)
The Memory DMA (MemDMA) controller provides memory-to-memory
DMA transfers among the ADSP-BF535 processor memory spaces. These
memory spaces include the Peripheral Component Interconnect (PCI)
address spaces, L1, L2, external synchronous, and asynchronous
memories.
The MemDMA controller consists of two channels—one for the source,
which is used to read from memory, and one for the destination, which is
used to write to memory. Both channels share a 16-entry, 32-bit FIFO.
The source DMA channel fills the FIFO; the destination DMA channel
empties it. The FIFO depth significantly improves throughput on block
transfers between internal and external memory. The FIFO supports 8-,
16-, and 32-bit transfers. However, 8- and 16-bit transfers use only part of
the 32-bit data bus for each transfer; therefore, the throughput for these
transfer sizes is less than for full, 32-bit DMA operations.
The MemDMA controller does not support autobuffer based DMA.
Transfers using the MemDMA controller must use descriptor based
DMA. Two separate linked lists of descriptor blocks are required—one for
the source DMA channel and one for the destination DMA channel. The
separation of control allows an off-chip host processor to manage one list
through the PCI port bus and the core processor to manage the other list.
For a detailed explanation of descriptor based DMA, see
“Descriptor
Based DMA” on page 9-3 .

Because the source and destination DMA channels share a single
FIFO buffer, the descriptor blocks must be configured to have the
same transfer count and data size.
It is preferable to activate interrupts on only one channel. This eliminates
ambiguity when trying to identify the channel (either source or destina-
tion) that requested the interrupt.