Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Sequencer Related Registers
4-6 ADSP-BF535 Blackfin Processor Hardware Reference
The 32-bit loop register sets are described in Table 4-2 .
System Configuration Register (SYSCFG)
The System Configuration Register (
SYSCFG
), shown in Figure 4-3 , con-
trols the configuration of the processor. This register is accessible only
from the Supervisor mode.
Table 4-2. Loop Registers
Registers Description Function
LC[1:0] Loop Counters Maintain a count of the remaining iterations of the
loop
LT[1:0] Loop Tops Hold the address of the first statement within a loop
LB[1:0] Loop Bottoms Hold the address of the last statement of the loop
Figure 4-3. System Configuration Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 X X X X X X X X X X X X X 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X X X X X X X X X
System Configuration Register (SYSCFG)
CCEN (Cycle-Counter Enable)
SSSTEP (Supervisor Single Step)
When set, a Supervisor excep-
tion is taken after each instruction
is executed. It applies only to
User mode, or when processing
interrupts in Supervisor mode. It
is ignored if the core is process-
ing an exception or higher-priority
event. If precise exception timing
is required, CSYNC must be
used after setting this bit.
CCEN must be set after PFPWR is
set (See chapter 20, Blackfin
Debug)
0 - Disable 64-bit, free-running
cycle counter
1 - Enable 64-bit, free-running
cycle counter
Reset = Undefined
SNEN (Self-Nesting Interrupt Enable)
0 - Disable self-nesting interrupts
1 - Enable self-nesting interrupts