Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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External Bus Interface Unit
1-12 ADSP-BF535 Blackfin Processor Hardware Reference
memory controller, and the PCI bus interface. DMA capable peripherals
include the SPORTs, SPIs, UARTs, USBs, and memory DMA controller.
Each individual DMA capable peripheral has at least one dedicated DMA
channel. DMA to and from PCI is accomplished via the memory DMA
channel.
To describe each DMA sequence, the DMA controller uses a set of param-
eters, called a
descriptor block . When successive DMA sequences are
needed, these descriptor blocks can be linked or chained together so the
completion of one DMA sequence autoinitiates and starts the next
sequence. The descriptor blocks include full 32-bit addresses for the base
pointers for source and destination, enabling access to the entire Blackfin
address space.
In addition to the dedicated peripheral DMA channels, there is a separate
memory DMA channel provided for transfers between the various
ADSP-BF535 system memories. This enables transfers of blocks of data
between any of the memories, including on-chip Level 2 memory, external
SDRAM, ROM, SRAM and flash memory, and PCI address spaces with
little processor intervention.
External Bus Interface Unit
The External Bus Interface Unit on the ADSP-BF535 processor interfaces
with a wide variety of industry-standard memory devices. The controller
consists of an SDRAM controller and an asynchronous memory
controller.
PC133 SDRAM Controller
The SDRAM controller provides an interface to up to four separate banks
of industry-standard SDRAM devices or DIMMs. Fully compliant with
the PC133 SDRAM standard, each bank can be configured to contain
between 16 and 128 Mbytes of memory.