Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 1-19
Introduction
• DMA operations with single cycle overhead
• Each SPORT can automatically receive and transmit multi-
ple buffers of memory data. The processor can link or chain
sequences of DMA transfers between a SPORT and mem-
ory. The chained DMA can be dynamically allocated and
updated through the descriptor blocks or DMA parameters
that set up the chain.
• Interrupts
• Each transmit and receive port generates an interrupt upon
completing the transfer of a data word or after transferring
an entire data buffer or buffers through DMA.
• Multichannel capability
• Each SPORT supports 128 channels and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
Serial Peripheral Interface (SPI) Ports
The ADSP-BF535 processor has two SPI-compatible ports that enable the
processor to communicate with multiple SPI-compatible devices.
The SPI interface uses three pins for transferring data: two data pins and a
clock pin. Two SPI chip select input pins let other SPI devices select the
processor, and fourteen SPI chip select output pins let the processor select
other SPI devices. The SPI select pins are reconfigured Programmable Flag
pins. Using these pins, the SPI ports provide a full duplex, synchronous
serial interface, which supports both master and slave modes and multi-
master environments.
Each SPI port baud rate and clock phase/polarities are programmable, and
each has an integrated DMA controller, configurable to support either
transmit or receive data streams.