Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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G-10 ADSP-BF535 Blackfin Processor Hardware Reference
External Bus Controller (EBC).
A component that provides arbitration between the EAB and EMB buses,
granting at most one requester per cycle.
External Mastered Bus (EMB).
A line or bus that allows the PCI to directly access internal L2 memory,
off-chip memory, and the system MMRs.
edge-sensitive interrupt.
A signal or interrupt that the processor detects if the input signal is high
(inactive) on one cycle and low (active) on the next cycle when sampled on
the rising edge of
CLKIN
.
Endian format.
The ordering of bytes in a multibyte number. The processor uses big
endian format—moves data starting with most-significant-bit and finish-
ing with least significant bit—in almost all instances. The two exceptions
are bit order for data transfer through the serial port and word order for
packing through the external port. For compatibility with little endian
(least significant first) peripherals, the processor supports both big and lit-
tle endian bit order data transfers. Also for compatibility little endian
hosts, the processor supports both big and little endian word order data
transfers.
external port.
A channel or port that extends the processors internal address and data
buses off-chip, providing the processor’s interface to off-chip memory and
peripherals.