Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Memory Architecture
6-42 ADSP-BF535 Blackfin Processor Hardware Reference
If both data banks are configured as cache,
DCBS
designates Address bit
A[14] or A[23] as the cache selector. Address bit A[14] or A[23] selects the
cache implemented by Data Bank A or the cache implemented by Data
Bank B.
• If
DCBS=0
, then
A[14]
is part of the address index , and all addresses
in which
A[14]=0
use Data Bank A. All addresses in which
A[14]=1
use Data Bank B.
• In this case,
A[23]
is treated as just another bit in the address that is
stored with the tag in the cache and compared for Hit/Miss pro-
cessing by the cache.
• If
DCBS=1
, then
A[23]
is part of the address index, and all addresses
where
A[23]=0
use Data Bank A. All addresses where
A[23]=1
use
Data Bank B.
• In this case,
A[14]
is treated as just another bit in the address that is
stored with the tag in the cache and compared for Hit/Miss pro-
cessing by the cache.
The result of choosing
DCBS=0
or
DCBS=1
is:
• If
DCBS=0
,
A[14]
selects Data Bank A instead of Data Bank B.
• Alternating 16 KB pages of memory map into each of the two
16 KB caches implemented by the two data banks. Consequently,
any data in the first 16 KB of memory could be stored
only in Data
Bank A. Any data in the next address range (16 KB through
32 KB)–1 could be stored
only in Data Bank B. Any data in the
next range (32 KB through 48 KB)–1 would be stored in Data
Bank A. Alternate mapping would continue.
• As a result, the cache operates as if it were a single, contiguous,
2-Way set-associative 32 KB cache. Each Way is 16 KB long and
all data elements having the same first 14 bits of address compete
for two entries that may be used to store them.