Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 1-7
Introduction
accessed through the External Bus Interface Unit (EBIU), provides
expansion with SDRAM, flash memory, and SRAM, optionally accessing
more than 768 Mbytes of physical memory.
The memory DMA controller provides high bandwidth data movement
capability. It can perform block transfers of code or data between the
internal L1/L2 memories and the external memory spaces, including PCI
memory space.
Internal (On-Chip) Memory
The ADSP-BF535 processor has four blocks of on-chip memory that pro-
vide high bandwidth access to the core:
• L1 instruction memory consisting of 16 Kbytes of 4-way set asso-
ciative cache memory. In addition, the memory may be configured
as an SRAM. This memory is accessed at full processor speed.
• L1 data memory, consisting of two banks of 16 Kbytes each. Each
L1 data memory bank may be configured as a 1- or 2-way set asso-
ciative cache or as an SRAM, and it is accessed at full speed by the
core.
• 4 Kbyte scratchpad RAM, which runs at the same speed as the L1
memories but is only accessible as data SRAM and cannot be con-
figured as cache memory.
• L2 SRAM memory array, which provides 256 Kbytes of high speed
SRAM at the full bandwidth of the core and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and data
required by the system design.