Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 250 / 1022

Memory Architecture
6-24 ADSP-BF535 Blackfin Processor Hardware Reference
Instruction Cache Management
The system DMA controller and the core DAGs cannot access the instruc-
tion cache directly. By a combination of instructions and the use of core
MMRs, it is possible to initialize the instruction tag and data arrays
indirectly and provide a mechanism for instruction cache test, initializa-
tion, and debug (See the Instruction Test Command Register in
Figure 6-9 on page 6-27 and Data Test Command Register in Figure 6-15
on page 6-49 .)
Instruction Cache Locking
The instruction cache has four independent lock bits (
ILOC[3:0
]) that
control each of the four Ways of the instruction cache. When the cache is
enabled, each sub-bank of L1 Instruction Memory is a Way. Setting the
lock bit for a specific Way prevents state transitions for all the lines in that
Way; that is, lines cannot change state from valid to invalid, or
vice versa .
Thus, setting the lock bit for a Way effectively prevents the Way from par-
ticipating in the replacement policy.
An example sequence is provided below to demonstrate how to lock down
Way0:
• If the code of interest may already reside in the instruction cache,
invalidate the entire cache first (for an example, see “Instruction
Cache Invalidation” on page 6-25 ).
• Disable interrupts, if needed, to prevent Interrupt Service Routines
(ISRs) from potentially corrupting the locked cache.
• Set the locks for the other Ways of the cache by setting
ILOC[3:1]
.
Only Way0 of the instruction cache can now be replaced by new
code.