Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Memory Architecture
6-20 ADSP-BF535 Blackfin Processor Hardware Reference
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Note that only valid cache lines (cache lines with their Valid bit
set) are included in the address tag compare operation. For cache
hits to occur:
• The instruction memory unit must be enabled and configured as
cache by setting bit 0 and bit 2 of the
IMEM_CONTROL
register.
• The CPLB must be enabled, and the page corresponding to the
instruction fetch address must be mapped as cacheable.
When a cache hit occurs, the target 64-bit instruction word is first sent to
the Instruction Alignment Unit where it is stored in one of two 64-bit
instruction buffers.
When a cache miss occurs, the instruction memory unit generates a cache
line fill access to retrieve the missing cache line from memory that is exter-
nal to the core. The address for the external memory access is the address
of the target instruction word. When a cache miss occurs, the core halts
until the target instruction word is returned from external memory.
Cache Line Fills
A cache line fill consists of fetching 32 bytes of data from memory. The
operation starts when the instruction memory unit requests a line-read
data transfer (a burst of four 64-bit words of data) on its external
read-data port. The address for the read transfer is the address of the target
instruction word. When responding to a line-read request from the
instruction memory unit, the L2 memory returns the target instruction
word first. After it has returned the target instruction word, the next three
words are fetched in sequential address order. This fetch will wrap around
if necessary, as shown in
Table 6-2 .