Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 13-45
PCI Bus Interface
Power Sequencing
The PCI interface operates on two power domains. The internal logic is
on the same power domain as the rest of the internal logic of the
ADSP-BF535 processor. The PCI I/O is powered through a dedicated set
of power pins. These two domains can operate at different voltage levels.
In general, it is recommended that power be applied to both domains at
the same time, or to the I/O power domain first then to the internal logic
power domain.
PCI Clock Requirements
The 33 MHz PCI clock requirements are >= 30 ns cycle time, with a max-
imum skew of <= 2 ns across all PCI component clock inputs. The clock
may be stopped, but only in the low state. This clock can be driven com-
pletely asynchronously with respect to the internal ADSP-BF535
processor’s clocks and
CLKIN
.