Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Memory Architecture
6-22 ADSP-BF535 Blackfin Processor Hardware Reference
Non-Cacheable Accesses
The line fill buffer is also used to support non-cacheable accesses. A
non-cacheable access consists of a single 64-bit word data transfer on the
instruction memory unit’s external read port. Non-cacheable accesses
include:
• External memory accesses performed while the instruction memory
unit is disabled
• External memory accesses performed while the instruction memory
unit is enabled and configured as SRAM
• Accesses to non-cacheable pages
A page is considered non-cacheable if the
CPLB_L1_CHBL
bit of the associ-
ated CPLB descriptor for the matching address is cleared.
Cache Line Replacement
When the instruction memory unit is configured as cache, bits 9 through
5 of the instruction fetch address are used as the index to select the cache
set for the tag-address compare operation. If the tag-address compare
operation results in a cache miss, the Valid bits for the selected set are
examined by a cache line replacement unit to determine the entry to use
for the new cache line, that is, whether to use Way0, Way1, Way2, or
Way3 (see the cache organization in
Figure 6-6 on page 6-18 ).
Table 6-3. Encoded Cache Ways
Line-Buffer Way [1:0] Cache Way
00 Way 0
01 Way 1
10 Way 2
11 Way 3