Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 319 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 7-7
Chip Bus Hierarchy
On-Chip L2 SRAM Memory Interface
The on-chip L2 SRAM memory block consists of 256 KB of fast, deter-
ministic access time memory. The L2 memory is unified; that is, it is
directly accessible by both the instruction core port and the data core
ports of the architecture. The L2 is organized as a multibank architecture
of single ported SRAMs, so that multiple accesses to different banks can
occur in parallel. The SBIU has two ports into the L2 memory, one dedi-
cated to core requests (Core L2), the other dedicated to system DMA and
PCI requests (Sys L2). For additional information about L2 memory, see
“Memory” on page 6-1 .
System Interfaces
The ADSP-BF535 processor system includes the peripheral set (Timers,
Real Time Clock, USB, programmable flags, UARTs, SPORTs, and
SPIs), the PCI controller, the external memory controller (EBIU), the
Memory DMA controller, and the interfaces between these, the system,
and the optional external (off-chip) resources. See
Figure 7-1 .
These sections describe the four on-chip interfaces between the system
and the peripherals:
• Peripheral Access Bus (PAB)
• DMA Access Bus (DAB)
• External Access Bus (EAB)
• External Mastered Bus (EMB)
There are also two primary chip pin buses, the PCI Bus and the External
Bus Interface Unit (EBIU). The PCI Bus is discussed in
“PCI Bus Inter-
face” on page 13-1 . The External Bus Interface Unit is discussed in
“External Bus Interface Unit” on page 18-1 .