Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SPORT Registers
11-36 ADSP-BF535 Blackfin Processor Hardware Reference
SPORTx Receive DMA Count (SPORTx_COUNT_RX)
Registers
The SPORT Receive DMA Count register, shown in Figure 11-20 , holds
the number of remaining words in the transfer. This is a read-only regis-
ter. It can be written in autobuffer mode.
SPORTx Receive DMA Next Descriptor Pointer
(SPORTx_NEXT_DESCR_RX) Registers
The SPORT Receive DMA Next Descriptor Pointer register, shown in
Figure 11-21 , maintains the 16 LSBs of the head address of the next DMA
descriptor block. Together, the
SPORTx_NEXT_DESCR_RX
and the
DB_NDBP
registers form the 32-bit head address of the next descriptor block. During
SPORT initialization, the programmer writes the head address of the first
DMA descriptor block to the Receive DMA Next Descriptor Pointer reg-
ister and then sets the
DEN
bit in the Transmit or Receive DMA
Configuration Registers.
Figure 11-20. SPORTx Receive DMA Count Registers
Table 11-19. SPORTx Receive DMA Count Register MMR Assignments
Register Name Memory-Mapped Address
SPORT0_COUNT_RX 0xFFC0 2A08
SPORT1_COUNT_RX 0xFFC0 2E08
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPORTx Receive DMA Count Registers (SPORTx_COUNT_RX)
Words Remaining in
Transfer[15:0]
Reset = 0x0000
RO. Writable in autobuffer mode.
For MMR
assignments, see
Table 11-19 .