Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 11-3
Serial Port Controllers
• Performs interrupt-driven, single word transfers to and from
on-chip memory under core control.
• Provides Direct Memory Access transfer to and from memory
under DMA Master control. DMA can be autobuffer based (a
repeated, identical range of transfers) or descriptor based (individ-
ual or repeated ranges of transfers with differing DMA parameters).
• Executes DMA transfers to and from on-chip memory. Each
SPORT can automatically receive and transmit an entire block of
data.
• Permits chaining of DMA operations for multiple data blocks.
• Has a multichannel mode for TDM interfaces. Each SPORT can
receive and transmit data selectively from channels of a time-divi-
sion-multiplexed serial bitstream multiplexed into up to 128
channels. This mode can be useful as a network communication
scheme for multiple processors.
• Operates with or without frame synchronization signals for each
data word, with internally generated or externally generated frame
signals, with active high or active low frame signals, and with either
of two configurable pulse widths and frame signal timing.
Table 11-1 shows the pins for each SPORT.
Table 11-1. Serial Port (SPORT) Pins
Pin Description
DTx Transmit Data
DRx Receive Data
TCLKx Transmit Clock
RCLKx Receive Clock
TFSx Transmit Frame Sync
RFSx Receive Frame Sync