Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-32 ADSP-BF535 Blackfin Processor Hardware Reference
The SDC does not support interleaved accesses. The bank address can be
thought of as part of the row address. The SDC also assumes that all
SDRAMs to which it interfaces have four internal banks. You cannot con-
nect two-bank (16 Mbit) SDRAMs to the interface.

Do not confuse the “SDRAM internal banks” which are internal to
the SDRAM and are selected with the bank address, with the four
“SDRAM banks,” or “external banks,” that are enabled by the
SMS[3:0]
pins.
Mode Register.
SDRAM devices contain an internal configuration register which allows
specification of the SDRAM device’s functionality. After power-up and
before executing a read or write to the SDRAM memory space, the appli-
cation must trigger the SDC to write the SDRAM’s mode register. The
write of the SDRAM’s mode register is triggered by writing a 1 to the
PSSE
bit in the SDRAM Memory Global Control register (
EBIU_SDGCTL
) and
then issuing a read or write transfer to the SDRAM address space. The ini-
tial read or write triggers the SDRAM power-up sequence to be run,
which programs the SDRAM’s mode register with the CAS latency from
the
EBIU_SDGCTL
register. This initial read or write to SDRAM takes many
cycles to complete. Note for most applications, the SDRAM power-up
sequence and writing of the mode register needs to be done only once.
Once the power-up sequence has completed, the
PSSE
bit should not be
set again unless a change to the mode register is desired.
Page Size.
Page size is the amount of memory which has the same row address and
can be accessed with successive read or write commands without needing
to activate another row. The page size can be calculated for 32-bit and
16-bit SDRAM banks with these formulas:
• 32-bit SDRAM banks: page size = 2
(CAW + 2)