Multichannel Operation
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ADSP-BF535 Blackfin Processor Hardware Reference
Window Size
The window size defines the range of the channels that can be enabled/dis-
abled in the current configuration. It can be any value in the range of 8 to
128, in increments of 8; the default value of 0 corresponds to a minimum
window size of 8 channels. Since the DMA buffer size is always fixed, it is
possible to define a smaller window size (for example, 32 bits), resulting in
a smaller DMA buffer size (in this example, 32 bits instead of 128 bits) to
save DMA bandwidth. The window size cannot be changed while the
SPORT is enabled.
Window Offset
The window offset specifies where in the 127-channel range to place the
start of the window. A value of 0 specifies no offset and permits using all
128 channels. As an example, a program could define a window with a
window size of 5 and an offset of 93. This 5-channel window would reside
in the range from 93 to 97. The window offset cannot be changed while
the SPORT is enabled.
If the combination of the window size and the window offset would place
the window outside of the range of the channel enable registers, none of
the channels in the frame are enabled, since this combination is invalid.
Other Multichannel Fields in SPORTx_TX_CONFIG,
SPORTx_RX_CONFIG
A multichannel frame contains more than one channel, as specified by the
window size and window offset; the multichannel frame is a combined
sequence of the window offset and the channels contained in the window.
The total number of channels in the frame is calculated by adding the
window size to the window offset.
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...