Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 11-53
Serial Port Controllers
When companding is enabled, valid data in the
SPORTx_RX
register is the
right justified, expanded value of the eight LSBs received and sign
extended. A write to
SPORTx_TX
causes the 16-bit value to be compressed
to eight LSBs (sign extended to the width of the transmit word) and writ-
ten to the internal transmit register. If the magnitude of the 16-bit value is
greater than the 13-bit A-law or 14-bit

-law maximum, the value is auto-
matically compressed to the maximum positive or negative value.
Clock Signal Options
Each SPORT has a transmit clock signal (
TCLK
) and a receive clock signal
(
RCLK
). The clock signals are configured by the
ICLK
and
CKFE
bits of the
SPORTx_TX_CONFIG
and
SPORTx_RX_CONFIG
registers. Serial clock frequency
is configured in the
SPORTx_TSCLKDIV
and
SPORTx_RSCLKDIV
registers.

The receive clock pin may be tied to the transmit clock if a single
clock is desired for both input and output.
Both transmit and receive clocks can be independently generated inter-
nally or input from an external source. The
ICLK
bit of the
SPORTx_TX_CONFIG
and
SPORTx_RX_CONFIG
registers determines the clock
source.
When
ICLK
=
1
, the clock signal is generated internally by the core and the
TCLK
or
RCLK
pin is an output. The clock frequency is determined by the
value of the serial clock divisor in the
SPORTx_TSCLKDIV
or
SPORTx_RSCLKDIV
registers.
When
ICLK
=
0
, the clock signal is accepted as an input on the
TCLK
or
RCLK
pins, and the serial clock divisors in the
SPORTx_TSCLKDIV
/
SPORTx_RSCLKDIV
registers are ignored. The externally
generated serial clock need not be synchronous with the core system clock.