Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 13-37
PCI Bus Interface
PCI Configuration Cache Line Size Register
(PCI_CFG_CLS)
The
PCI_CFG_CLS
register, shown in Figure 13-20 , holds the cache line size
from the PCI configuration registers. It is writable from the PCI and from
the EAB side. It is unused because the memory write Invalidate (
MWINV
)
commands are disabled in the control register and the Inbound Cacheline
Wrap is not supported by the ADSP-BF535 processor. For more informa-
tion, see the PCI Local Bus Specification Rev. 2.2.
Figure 13-19. PCI Configuration Memory Latency Timer Register
Figure 13-20. PCI Configuration Cache Line Size Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCI Configuration Memory Latency Timer Register (PCI_CFG_MLT)
Latency Timer[7:2]
Reset = 0x0000 0000
Latency Timer[1:0] - RO
0xEEFF FF28
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCI Configuration Cache Line Size Register (PCI_CFG_CLS)
Cache Line Size[7:0]
Reset = 0x0000 0000
0xEEFF FF2C