Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Interface Signals
10-4 ADSP-BF535 Blackfin Processor Hardware Reference
In a multimaster or multidevice ADSP-BF535 environment where multi-
ple ADSP-BF535 processors are connected via their SPI ports, all
MOSI
pins are connected together, all
MISO
pins are connected together, and all
SCK
pins are connected together.
For a multislave environment, the ADSP-BF535 processor can make use
of 14 programmable flags,
PF2
–
PF15
, that are dedicated SPI slave select
signals for the SPI slave devices. SPI0 and SPI1 each have seven available
slave select signals.

At reset, the SPI is disabled and configured as a slave.
Interface Signals
The following sections discuss the SPI signals.
Serial Peripheral Interface Clock Signal (SCK)
The
SCK
signal is the SPI clock signal. This control signal is driven by the
master and controls the rate at which data is transferred. The master may
transmit data at a variety of baud rates.
SCK
cycles once for each bit trans-
mitted. It is an output signal if the device is configured as a master, and an
input signal if the device is configured as a slave.
The
SCK
signal is a gated clock that is active during data transfers only for
the length of the transferred word. The number of active clock edges is
equal to the number of bits driven on the data lines. Slave devices ignore
the serial clock if the Serial Peripheral Slave Select Input (
SPISS
) is driven
inactive (high).
The
SCK
signal is used to shift out and shift in the data driven on the
MISO
and
MOSI
lines. The data is always shifted out on active edges of the clock
and sampled on inactive edges of the clock. Clock polarity and clock phase
relative to data are programmable in the SPIx Control register
(SPIx_CTL)
and define the transfer format.