Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 12-3
UART Port Controller
Consistent with industry standard interfaces, multiple registers are
mapped to the same address location. The Divisor Latch registers
(
UARTx_DLH
and
UARTx_DLL
) share their addresses with the Transmit Hold-
ing registers (
UARTx_THR
), the Receive Buffer registers (
UARTx_RBR
), and the
Interrupt Enable registers (
UARTx_IER
). The Divisor Latch Access bit
(
DLAB
) in the Line Control Register (
UARTx_LCR
) controls which sets of reg-
isters are accessible at a given time.
UARTx Line Control Registers (UARTx_LCR)
The UARTx Line Control register (
UARTx_LCR
) controls the format of
received and transmitted character frames. Figure 12-2 shows the bits in
this register.
Figure 12-2. UARTx Line Control Registers
7 6 5 4 3 2 1 0
0 0 0 0 0 0
Reset = 0x00
0
0
DLAB (Divisor Latch Access)
1 - Enables access to UARTx_DLL
and UARTx_DLH
0 - Enables access to UARTx_THR/
UARTx_RBR and UARTx_IER
SB (Set Break)
0 - No force
1 - Force TX pin to 0
SP (Stick Parity)
Forces parity to defined value if set and PEN = 1
EPS = 1, parity transmitted and checked as 0
EPS = 0, parity transmitted and checked as 1
EPS (Even Parity Select)
1 - Even parity
0 - Odd parity when PEN = 1 and SP = 0
WLS[1:0] (Word Length Select)
00 - 5 bit word
01 - 6 bit word
10 - 7 bit word
11 - 8 bit word
STB (Stop Bits)
1 - 2 stop bits for non-5-bit word length or
1 1/2 stop bits for 5-bit word length
0 - 1 stop bit
PEN (Parity Enable)
1 - Transmit and check parity
0 - Parity not transmitted or checked
UARTx Line Control Registers (UARTx_LCR)
For MMR assignments,
see
Table 12-1 .