Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-83
Memory

When accessing memory-mapped devices that have state dependen-
cies on the number of read or write operations on a given address
location, disable interrupts before performing the load or store
operation.
Working With Memory
This section contains information about alignment of data in memory and
memory operations that support semaphores between tasks. It also con-
tains a brief discussion of MMR registers and a core MMR programming
example.
Alignment
Unaligned memory operations are not directly supported. An unaligned
memory reference generates a Misaligned Access exception event
(see
“Exceptions” on page 4-38 ). However, because some data streams,
such as 8-bit video data, can properly be unaligned in memory, alignment
exceptions may be disabled by using the
DISALGNEXCPT
instruction. More-
over, some instructions in the Quad 8-Bit group automatically disable
alignment exceptions.
For shared data, software must provide cache coherency support as
required. To accomplish this, use the
FLUSH
instruction (see “Data Cache
Control Instructions” on page 6-47 ), and/or explicit line invalidation
through the core MMRs (see “ICPLB Address Registers
(ICPLB_ADDRx)” on page 6-71 ).
Atomic Operations
Atomic operations are used to provide non-interruptible memory opera-
tions in support of semaphores between tasks.