Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 9-9
Direct Memory Access
• If the descriptor block is the last one in a linked list or the
only one (that is, a standalone transfer sequence), the Next
Descriptor Pointer within the descriptor block must point
to a memory location that contains a data value with bit 15
set to 0 (0xxx xxxx xxxx xxxx). If bit 0 is a 1 (0xxx xxxx xxxx
xxx1), the DMA channel is still enabled, but stalled, and the
remaining FIFO values are not discarded. This allows the
DMA engine to finish transferring the remaining values in
the FIFO.
• Because of this requirement, the Next Descriptor Pointer
can point to the base address ( BASE +0) of the current DMA
descriptor block. (After the DMA transfer sequence, bit 15
of the DMA Configuration Word is cleared, returning own-
ership to the processor. If ownership returns to the
processor, the DMA channel is still enabled but stalls after
the DMA transfer.)
2. Write the lower 16 bits (LSBs) of the descriptor block base address
(the first descriptor block if in a linked list), BASE +0, to the Next
Descriptor Pointer register of the appropriate peripheral.
3. Set the DMA Enable bit in the appropriate peripheral’s DMA
Configuration register.
• This final write is needed only if this DMA descriptor block
is for a standalone transfer sequence or the first one in a
linked list.
Descriptor-Based DMA Operation
Upon detecting the assertion of the DMA Enable bit in the peripheral’s
DMA Configuration register, the DMA channel fetches the first element
from the descriptor block, the DMA Configuration Word, and copies it to