Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 19-3
System Design
Managing Core and System Clocks
The ADSP-BF535 processor produces a 1x-31x multiplication of the
clock input provided on the
CLKIN
pin to generate the core clock (
CCLK
).
Additionally, the system clock (
SCLK
) is derived from the core clock. This
clock is based on a divider ratio that is programmed via the
SSEL
bit set-
tings. For detailed information about how to set and change
CCLK
and
SCLK
frequencies, see “Dynamic Power Management” on page 8-1 .
Designing for Multiplexed Clock Pins
The ADSP-BF535 processor’s
MSEL6–0
pins are multiplexed with the
PF6–
0
pins;
SSEL1–0
pins are multiplexed with the
PF9–8
pins. During reset,
these pins act as multiplier selects when in multiplier mode and as pro-
grammable flags after reset. This multiplexing influences system design as
follows.
• For systems selecting Bypass mode during reset,
MSELx
pin states do
not need to be managed during reset. The multiplexed nature of
these pins does not influence system design for the
PFx
pins.
• For systems using Multiplier mode during reset and not using
PFx
pins at runtime, use pull-up or pull-down resistors to select the
MSELx
and
SSELx
values. Do not leave these pins unconnected.
• For systems using Multiplier mode during reset and using the
PFx
pins at runtime, use pull-up or pull-down resistors to select the
MSELx
values during reset. Ensure that the system permits the
MSELx
and
SSELx
pins to stabilize to a valid multiplier value in compli-
ance with the timing for
RESET
in the data sheet.