ADSP-BF535 Blackfin Processor Hardware Reference
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Direct Memory Access
Autobuffer Based DMA
Autobuffer based DMA operates like descriptor based DMA except that it
does not require descriptors in memory. In autobuffer mode, DMA con-
trol registers are writable and programmed directly by the processor to
initiate a DMA transfer sequence. Upon completion of the transfer
sequence, the control registers are reloaded with their original setup values
for the next transfer. This effectively creates a circular buffer that contin-
ues to transfer data until disabled by clearing the DMA Enable bit in the
peripheral’s DMA Configuration register. If enabled, interrupts are gener-
ated at the halfway and completion points in the transfer sequence. For
more information about peripheral interrupts, see the appropriate periph-
eral chapter.
Setting Up Autobuffer Based DMA
The following steps illustrate the typical sequence for setting up autobuf-
fer based DMA.
1. Set the Autobuffer Enable bit in the DMA Configuration register.
2. Initialize the DMA Transfer Count, DMA Start Address High, and
DMA Start Address Low registers.
3. Write to the DMA Configuration register, configuring the DMA
transfer and setting the DMA Enable bit.
This final write starts the autobuffer based DMA transfer sequence.
To disable autobuffering, clear the DMA Enable bit in the Config-
uration register. Clearing the bit during active operation will stop
the current single or burst transfer, but it will not cause a DMA
error abort as it would for descriptor based DMA. The Autobuffer
Enable bit in the DMA Configuration register can then be cleared.
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...