Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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DMA Control Registers
9-16 ADSP-BF535 Blackfin Processor Hardware Reference
Upon detecting that the DMA Enable bit is cleared, the DMA channel
completes the current single or burst transfer and disables DMA. After the
bit is cleared, the DMA Start Address and DMA Transfer Count registers
can be used to monitor the status of the DMA transfers.
DMA Control Registers
The registers in this section are a generic representation of the actual
peripheral DMA control registers, which are listed in
Table 9-12 on
page 9-30 . The word “peripheral” is used in the register name in place of
the specific peripheral name.
Peripheral DMA Configuration Register
The peripheral’s DMA Configuration register determines whether DMA
is enabled and performs other essential DMA functions, including func-
tions that are peripheral dependent (see
Figure 9-5 ).
The DMA Enable bit enables and activates a DMA channel to begin load-
ing a descriptor block from memory. The processor should write the
DMA Enable bit only during DMA channel initialization and in activat-
ing or terminating autobuffer mode. For descriptor based DMA, if the
processor resets this bit during active operation, the DMA channel termi-
nates with an error condition (see
“DMA Abort Conditions” on
page 9-44 ).
The Buffer Clear bit is used to clear the DMA buffer and should be
accessed only when a DMA channel is not enabled.

The Buffer Clear bit should not be set when using autobuffer
mode.