Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Event Vector Table
4-36 ADSP-BF535 Blackfin Processor Hardware Reference
Emulation
An emulation event causes the processor to enter Emulation mode, in
which instructions are read from the JTAG interface. It is the highest pri-
ority interrupt to the core.
For detailed information about emulation, see “Blackfin Processor’s
Debug” on page 20-1 .
Reset
The reset interrupt (
RST
) can be initiated via the
RESET
pin or through
expiration of the Watchdog timer. The
EVT[1]
register holds the address
at which the processor begins execution after reset. This location differs
from that of other interrupts in that its content is read-only. Writes to this
address have no effect.
The core has an output that indicates that a double-fault has occurred.
This is a non-recoverable state. The SIC (via
SIC_IMASK
) can be pro-
grammed to send a reset request if a double-fault condition is detected.
Subsequently, the reset request forces a system reset for core and
peripherals.
EVT10 Interrupt 10 IVG10 0xFFE0 2028
EVT11 Interrupt 11 IVG11 0xFFE0 202C
EVT12 Interrupt 12 IVG12 0xFFE0 2030
EVT13 Interrupt 13 IVG13 0xFFE0 2034
EVT14 Interrupt 14 IVG14 0xFFE0 2038
EVT15 Interrupt 15 IVG15 0xFFE0 203C Lowest priority.
Table 4-9. Core Event Vector Table (Cont’d)
Event Number Event Class Name MMR Location Notes