Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SPI Registers
10-16 ADSP-BF535 Blackfin Processor Hardware Reference
Sticky bits can only be cleared by writing a 1 to them. Writing 0 does not
have any effect on a sticky bit. This is known as a write-1-to-clear (W1C)
bit.
The transmit buffer becomes full after it is written to. It becomes empty
when a transfer begins and the transmit value is loaded into the shift regis-
ter. The receive buffer becomes full at the end of a transfer when the shift
register value is loaded into the receive buffer. It becomes empty when the
receive buffer is read.
Figure 10-7. SPIx Status Register
Table 10-7. SPIx Status Register MMR Assignments
Register Name Memory-Mapped Address
SPI0_ST 0xFFC0 3004
SPI1_ST 0xFFC0 3404
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset = 0x0001
SPIF (SPI Finished) - RO
Set when SPI single word
transfer complete
MODF (Mode Fault Error) -
W1C
Set in a master device when
some other device tries to
become the master
TXE (Transmission Error) -
W1C
Set when transmission
occurred with no new data in
SPIx_TDBR
TXS (SPIx_TDBR Data Buf-
fer Status) - RO
0 - Empty
1 - Full
SPIx Status Register (SPIx_ST)
TXCOL (Transmit Collision Error) - W1C
When set, corrupt data may
have been transmitted
SPIx_RDBR Data Buffer Status - RO
0 - Empty
1 - Full
RBSY (Reception Error) - W1C
Set when data is received with
receive buffer full
For MMR
assignments,
see
Table 10-7 .