Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 854 / 1022

Cycle Counter
20-24 ADSP-BF535 Blackfin Processor Hardware Reference
Cycle Counter
The cycle counter counts
CCLK
cycles while the program is executing. All
cycles, including execution, wait state, interrupts, and events, are counted
while the processor is in User or Supervisor mode, but the cycle counter
stops counting in Emulator mode.
The cycle counter is a 64-bit counter that increments every cycle. The
count value is stored in two 32-bit registers,
CYCLES
and
CYCLES2
. The
least significant 32 bits are stored in
CYCLES.
The most significant 32 bits
are stored in
CYCLES2
.

To ensure the correct cycle count, a read from
CYCLES
must occur
before reading from
CYCLES2
.
In User mode, these two registers may be read, but not written. In Super-
visor and Emulator modes, they are read/write registers.
To enable the cycle counters, set the
CCEN
bit in the
SYSCFG
register.
This example shows how to turn on the cycle counter:
r2 = 0 ;
cycles = r2 ;
cycles2 = r2 ;
r2 = SYSCFG ;
bitset(r2, 1) ;
SYSCFG = r2 ;
/* Insert code to be benchmarked */
0x75 Store to load forwarding
0x80 Stall cycles because of EX stage data hazards
Table 20-11. Event Monitor Table (Cont’d)
PFMONx Fields Events That Cause the PFCNTRx Counter Registers
to Increment