Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Register Files
2-6 ADSP-BF535 Blackfin Processor Hardware Reference

In the ADSP-BF535 processor, a word is 32 bits long; H denotes
the high order 16 bits of a 32-bit register; L denotes the low order
16 bits of a 32-bit register. For example,
A0.W
contains the lower
32 bits of the 40-bit
A0
register;
A0.L
contains the lower 16 bits of
A0.W
, and
A0.H
contains the upper 16 bits of
A0.W
.
Data Register File
The Data Register File consists of eight registers, each of which are 32 bits
wide. Each register may be viewed as a pair of independent 16-bit regis-
ters. Each is denoted as the low half or high half. Thus the 32-bit register
R0
may be regarded as two independent register halves,
R0.L
and
R0.H
Two separate buses connect the register file to the L1 data memory, each
bus being 32 bits wide. Transfers between the Data Register File and the
data memory can move up to four 16-bit words of valid data in each cycle.
Accumulator Registers
In addition to the Data Register File, the ADSP-BF535 processor has two
dedicated, 40-bit accumulator registers. Each may be referred to as its
16-bit low half (
An.L
) or high half (
An.H
) plus its 8-bit extension (
An.X
),
or as a 32-bit register (
An.W
) consisting of the lower 32 bits, or as a com-
plete 40-bit result register (
An
).
Pointer Register File
The general-purpose address Pointer registers, also called the P-registers,
are organized as:
• A 6-entry, P-register file
P[5:0]
• A Frame Pointer (
FP
) used to point to the current procedure’s acti-
vation record