Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Programmable Flag Memory-Mapped Registers (MMRs)
15-2 ADSP-BF535 Blackfin Processor Hardware Reference
Each
PFx
pin is represented by a bit in each of the four registers. Writing a
1 to a bit in a mask set register enables interrupt generation for that
PFx
pin, while writing a 1 to a bit in a mask clear register disables interrupt
generation for that
PFx
pin.
The
PFx
pins are multiplexed for use by the Serial Port Interface (SPI) and
Phase Locked Loop (PLL) circuitry. Refer to the “SPI” and the “Dynamic
Power Management” chapters for more information.
Programmable Flag Memory-Mapped
Registers (MMRs)
The programmable flag (
PFx
) registers are part of the system memory-
mapped registers (MMRs). The addresses of the programmable flag
MMRs appear in Appendix B. Core access to the flag configuration regis-
ters is through the system bus.
Flag Direction Register (FIO_DIR)
The Flag Direction register, shown in Figure 15-1 , is a read-write register.
Each bit position corresponds to a
PFx
pin. A logic 1 configures a
PFx
pin
as an output, and a logic 0 configures a
PFx
pin as an input. The reset
value of this register is 0x0000, making all
PFx
pins inputs upon reset.
Flag Set (FIO_FLAG_S) and Flag Clear
(FIO_FLAG_C) Registers
The Flag Set and Flag Clear registers, shown in Figure 15-2 and
Figure 15-3 , are used to sense the value of the
PFx
pins defined as inputs,
to set the state of
PFx
pins defined as outputs, and to clear interrupts gen-
erated by the
PFx
pins. Each
PFx
pin is represented by a bit in each of these
registers.