Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 4-21
Program Sequencer
9. When the interrupt service routine for Interrupt A has been exe-
cuted, the RTI instruction clears the appropriate
IPEND
bit.
However, the relevant
SIC_ISR
bit is not cleared unless the inter-
rupt service routine clears the mechanism that generated Interrupt
A, or if the process of servicing the interrupt clears this bit.
It should be noted that emulation, reset, NMI, and exception events, as
well as hardware error (
IVHW
) and core timer (
IVTMR
) interrupt requests,
enter the interrupt processing chain at the
ILAT
level and are not affected
by the system-level interrupt registers (
SIC_IWR
,
SIC_ISR
,
SIC_IMASK
,
SIC_IARx
).
If multiple interrupt sources share a single core interrupt, then the ISR
must identify the peripheral that generated the interrupt. The ISR may
then need to interrogate the peripheral to determine the appropriate
action to take.
Figure 4-5. Interrupt Processing Block Diagram
PERIPHERAL
I NTERRU PT
REQ UESTS
CORE
EVENT
VECTO R
TABLE
( EVT[15:0]
)
CORE
INTERR UPT
MASK
(IMASK)
CORE
STATUS
(ILAT)
CORE
PENDING
(IPEND)
ASSIGN
SYSTEM
PRIORITY
(SIC_IAR0.. 2
)
SYSTEM
INTERR UPT
MASK
(SIC_IMASK
)
SYSTEM
STATUS
(SIC_ISR)
SYSTEM
WAKE-UP
(SIC_I WR )
CORE EVENT CONTROLLER SYSTEM INTERRUPT CONTROLLER
EMU
RESET
NMI
EVX
IV TMR
IVHW
TO DYN AMI C POWER
MA NAGEME NT
CONTROLLER
N ote: N am es in parentheses are m em ory -m apped regis ters .
“INTERRUPT
A”