Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 532 / 1022

UARTx Control and Status Registers
12-10 ADSP-BF535 Blackfin Processor Hardware Reference
Because of the destructive nature of these read operations, special care
should be taken. See
“Speculative Load Execution” on page 6-81 and
“Conditional Load Behavior” on page 6-82 for more information.
UARTx Divisor Latch Registers (UARTx_DLL,
UARTx_DLH)
The bit rate is characterized by the system clock (
SCLK
) and the 16-bit
Divisor. The Divisor is split into the Divisor Latch Low Byte register
(
UARTx
_
DLL
) and the Divisor Latch High Byte register (
UARTx_DLH
), as
shown in Figure 12-8 . These registers form a 16-bit divisor. The baud
clock is divided by 16 so that:
BAUD RATE = SCLK/(16

Divisor)
Divisor = 65,536
when
UARTx_DLL
=
UARTx_DLH = 0
Figure 12-7. UARTx Interrupt Identification Registers
Table 12-6. UARTx Interrupt Identification Register MMR Assignments
Register Name Memory-Mapped Address
UART0_IIR 0xFFC0 1804
UART1_IIR 0xFFC0 1C04
0 0 0 0 0
NINT (Pending interrupt)
7 6 5 4 3 2 1 0
1 0
Reset = 0x01
0
UARTx Interrupt Identification Registers (UARTx_IIR)
RO
STATUS[1:0]
0 - Interrupt pending
1 - No interrupt pending
00 - Modem status interrupt. Read UARTx_MSR to clear.
01 - UARTx_THR empty. Write UARTx_THR or read
UARTx_IIR to clear.
10 - Receive data ready. Read UARTx RBR to clear.
11 - Receive line status. Read UARTx_LSR to clear.
For MMR assignments,
see
Table 12-6 .