Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-55
Memory
memory is configured as non-cacheable. To illustrate the concept of L2
latency with cache off, simple instructions are used that do not require
additional external data fetches. In this case, consecutive instructions are
issued on consecutive cycles if multiple instructions are brought into the
core in a given fetch. Note also that two of the seven cycles are hidden by
the Blackfin processor pipeline. This is because the sequencer fetches the
next 64-bit fill before executing all available instructions obtained from
the previous fill.
Off-Chip L2 Memory
The external memory space is shown in Figure 20-1 on page 20-5. Four of
the memory regions are dedicated to SDRAM support. The size of each
SDRAM bank is programmable. Each SDRAM bank can range in size
from 16 MB to 128 MB. The start address of bank 0 is 0x0000 0000. The
start addresses of banks 1, 2, and 3 follow contiguously from the previous
Figure 6-20. L2 Latency With Cache Off
64 BITS
E
F
G
H
A B C D
I
J
K L
A B C D
INSTRUCTION ALIGNMENT UNIT
E
F G H
A
B C D
INSTRUCTION ALIGNMENT UNIT
T+7 ABCD READY
TO EXECUTE
T+8 A EXECUTES
T+9 B EXECUTES
T+10 C EXECUTES
T+11 D EXECUTES
L2 MEMORY
T+16 E EXECUTES
E F G H
I
J K L
INSTRUCTION ALIGNMENT UNIT
CYCLES T+7
EACH INSTRUCTION FETCH IS 64 BITS
T