Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-85
Memory
All MMRs are accessible only in Supervisor mode. Access to MMRs in
User mode generates an Illegal Access exception.
All core MMRs are read and written using 32-bit-aligned accesses. How-
ever, some MMRs have fewer than 32 bits defined. In this case, the
unused bits are reserved.
Accesses to nonexistent MMRs generate an exception. The system ignores
writes to read-only MMRs.
Appendix A provides a summary of all Core MMRs. Appendix B provides
a summary of all System MMRs.

To ensure upward compatibility with future implementations,
write back the value that is read for reserved bits in a register.
Core MMR Programming Code Example
Core MMRs may be accessed only as aligned 32-bit words. Non-aligned
access to MMRs generates an exception event.
Listing 6-5 shows the
instructions required to manipulate a generic core MMR.
Listing 6-5. Core MMR Programming
CLI R0; /* stop interrupts and save IMASK */
P0 = MMR_BASE; /* 32-bit instruction to loadbase of MMRs */
R1 = [P0 + TIMER_CONTROL_REG]; /* get value of control reg */
BITSET R1, #N; /* set bit N */
[P0 + TIMER_CONTROL_REG] = R1; /* restore control reg */
CSYNC; /* assures that the control reg is written */
STI R0; /* enable interrupts */
In the code listing, CLI saves the contents of the
IMASK
register and dis-
ables interrupts by clearing
IMASK
, while
STI
restores the contents of the
IMASK
register, thus enabling interrupts. The instructions between
CLI
and
STI
are not interruptible.