Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 162 / 1022

Loops and Sequencing
4-16 ADSP-BF535 Blackfin Processor Hardware Reference
The zero-overhead loop hardware provides efficient loops without the
overhead of additional instructions to branch, test a condition, or decre-
ment a counter. If the effective range of the loop needs to be larger than
that shown in
Table 4-5 , the loop can be set up manually by loading the
LCx
,
LTx
, and
LBx
registers manually.
The code example in Listing 4-1 shows a loop that contains two instruc-
tions and iterates 32 times.
Listing 4-1. Loop
P5 = 0x20 ;
LSETUP ( lp_start, lp_end ) LCO = P5 ;
lp_start:
R5 = R0 + R1(ns) || R2 = [P2++] || R3 = [I1++] ;
lp_end: R5 = R5 + R2 ;
Two sets of loop registers are used to manage two nested loops:
•
LC[1:0]
– the Loop Count registers
•
LT[1:0]
– the Loop Top address registers
•
LB[1:0]
– the Loop Bottom address registers
When executing an
LSETUP
instruction, the Program Sequencer loads the
address of the loop’s last instruction into
LBx
and the address of the loop’s
first instruction into
LTx
. The top and bottom addresses of the loop are
computed as PC-relative addresses from the
LSETUP
instruction plus an
offset. In each case, the offset value is added to the location of the
LSETUP
instruction.
LC0
and
LC1
are unsigned 32-bit registers supporting 2
32
–1 iterations
through the loop.