Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-74 ADSP-BF535 Blackfin Processor Hardware Reference
The read buffer is invalidated if any of these things occur:
• A cache line fill misses the read buffer.
• A write is done to any word in the line that is stored in the read
buffer.
• Prefetching is disabled (
PFE
=
0
in the SDRAM Memory Global
Control register).
Cache line fills always start at the address that missed in the cache. This
word is referred to as the critical word. For a cache line fill to have a par-
tial read buffer hit, the address of the critical word of the line being filled
must be in the read buffer.
A prefetch may be interrupted; therefore, it is possible to have a partially
filled read buffer. Words that are successfully prefetched into the read buf-
fer are considered valid words. All valid words which follow the critical
word in a line wrapping manner are counted as read buffer hits. For exam-
ple, prefetch begins and stores words 7, 0, 1, 2, and 3 into the read buffer,
and then it is interrupted. If the critical word of a cache line fill is word 3,
then only word 3 is a read buffer hit, since word 4 is not a valid word in
the read buffer. If the critical word of a cache line fill is word 7 in the same
prefetch, than all five words in the read buffer (words 7, 0, 1, 2, 3) would
be read-buffer hits. In this case, the maximum throughput of 1 word per
cycle is achieved.
Prefetch accesses are started only after a cache line fill access occurs. The
address of the first prefetch read is always the corresponding address of the
current critical word in the next line. For example, if a cache line fill access
starts with word 5, then the next prefetch would be from word 5 in the
following line.