Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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System Interfaces
7-10 ADSP-BF535 Blackfin Processor Hardware Reference
• PCI Port
• Asynchronous Memory Controller (AMC)
• SDRAM Controller (SDC)
• Memory DMA Controller
• SBIU
DMA Bus (DAB)
The DAB provides a means for DMA capable peripherals to gain access to
on-chip and off-chip memory with little or no degradation in core band-
width to memory.
DAB Arbitration
There are 8 DMA capable peripherals in the ADSP-BF535 processor sys-
tem. Twelve DMA channels and bus masters support these devices. The
peripheral DMA controllers can transfer data between peripherals and one
of:
• Internal memory (L1 or L2 memory, through SBIU)
• External memory (EAB, through SBIU)
Both the read and write channels of the Memory DMA controller access
their descriptor lists through the DAB.
The DAB has priority over the core processor on arbitration into L1 con-
figured as SRAM and L2. For off-chip memory, the core has priority over
the DAB on the EAB bus. The ADSP-BF535 processor uses a fixed prior-
ity arbitration policy on the DAB.
Table 7-2 shows the arbitration
priority.