Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Serial Communications
12-2 ADSP-BF535 Blackfin Processor Hardware Reference
Serial Communications
The UART follows an asynchronous serial communication protocol with
these options:
• 5 – 8 data bits
• 1, 1½, or 2 stop bits
• None, even, or odd parity
• Baud rate =
SCLK/(16 x Divisor)
, where
SCLK
is the system clock
frequency and Divisor can be a value from 1 to 65536
All data words require a start bit and at least one stop bit. With the
optional parity bit, this creates a 7- to 12-bit range for each word. Data is
always transmitted and received least significant bit (LSB) first.
Figure 12-1 shows a typical physical bit stream measured on the TX pin.
UARTx Control and Status Registers

The ADSP-BF535 processor provides a set of PC-style industry
standard control and status registers for each UART. These MMRs
are byte-wide registers that are accessed as 16-bit words with the
most significant byte zero filled.
Figure 12-1. Bit Stream on the TX Pin
Start bit Parity Bit (optional, odd or even)
Stop bit(s) Data bits
D0 D1 D2 D3 D4 D5 D6 D7
LSB