Clock and Frame Sync Frequencies
11-50
ADSP-BF535 Blackfin Processor Hardware Reference
Use the following equations to determine the correct value of
xFSDIV
,
given the serial clock frequency and desired frame sync frequency:
SPxTFSCLK frequency = (CLKOUT frequency) / (SPORTx_ 1
)
SPxRFSCLK frequency = (CLKOUT frequency) / (SPORTx_ 1
)
The frame sync would thus be continuously active if
xFSDIV=0
. However,
the value of
xFSDIV
should not be less than the serial word length minus
one (the value of the
SLEN
field in the transmit or receive control register);
a smaller value of
xFSDIV
could cause an external device to abort the cur-
rent operation or have other unpredictable results. If the SPORT is not
being used, the
xFSDIV
divisor can be used as a counter for dividing an
external clock or for generating a periodic pulse or periodic interrupt. The
SPORT must be enabled for this mode of operation to work.
Maximum Clock Rate Restrictions
Externally generated late transmit frame syncs also experience a delay from
arrival to data output, and this can limit the maximum serial clock speed.
See
ADSP-BF535 Blackfin Embedded Processor Data Sheet
for exact timing
specifications.
Be careful when operating with externally generated clocks near the
frequency of
SCLK
/2. There is a delay between the clock signal’s
arrival at the
TCLK
pin and the output of the data, and this delay
may limit the receiver’s speed of operation. See
ADSP-BF535
Blackfin Embedded Processor Data Sheet
for exact timing
specifications. At full speed serial clock rate, the safest practice is to
use an externally generated clock and externally generated frame
sync (
ICLK=0
and
IRFS=0
).
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...