Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-70 ADSP-BF535 Blackfin Processor Hardware Reference
SDC Operation
The ADSP-BF535 processor’s SDC uses a burst length = 1 for read and
write operations. Whenever a page miss occurs, the SDC executes a Pre-
charge command followed by a Bank Activate command before executing
the Read or Write command. If there is a page hit, the Read or Write
command can be given immediately without requiring the Precharge
command.
For SDRAM Read commands, there is a latency from the start of the Read
command to the availability of data from the SDRAM, equal to the CAS
latency. This latency is always present for the first read in a burst and for
any single read transfer. Subsequent reads in a burst do not have latency.
A programmable refresh counter is provided. It can be programmed to
generate background Auto-Refresh cycles at the required refresh rate based
on the clock frequency used. The refresh counter period is specified with
the
RDIV
field in the SDRAM Refresh Rate Control register.
To allow Auto-Refresh commands to execute in parallel with any AMC
access, a separate
A10
pin (
SA10
) is provided. All the SDRAM internal
banks are precharged before issuing an Auto-Refresh command, and all
external banks are refreshed at the same time. For more information, see
“Executing a Parallel Refresh Command” on page 18-47 .
SDC Configuration
After an ADSP-BF535 processor is reset, the SDC clocks are enabled;
however, the SDC must be configured and initialized. Before program-
ming the SDC and executing the power-up sequence, ensure the clock to
the SDRAM is enabled after the power has stabilized for the proper
amount of time (as specified by the SDRAM). In order to set up the SDC
and start the SDRAM power-up sequence for the SDRAMs, the SDRAM
Refresh Rate Control register (
EBIU_SDRRC
), the SDRAM Memory Bank
Control register (
EBIU_SDBCTL
), and SDRAM Memory Global Control