Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 633 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 14-25
USB Device
The
USBD_DMAEN
bit indicates the DMA-enabled and active status.
DMA Master Channel Base Address Low Register
(USBD_DMABL)
This register, Figure 14-12 , contains the low order bits of the base address
for the memory block to be accessed for USB buffers.
To produce a physical address on a per-transfer basis, the DMA master
channel replaces bits [10:0] with an endpoint specific offset value. Bits
[10:0] always read back 0.
Figure 14-11. DMA Master Channel Configuration Register
Figure 14-12. DMA Master Channel Base Address Low Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA Master Channel Configuration Register (USBD_DMACFG)
DMA configuration register. USBD_IOE bit has no effect on DMA transactions.
0 - DMA master channel
disabled
1 - DMA master channel
enabled
USBD_IOC - RO
USBD_DMABC
USBD_DMAEN
USBD_DMABS[1:0] - RO
Number of words in FIFO
00 - DMA FIFO has 1 to 15 bytes
01 - DMA FIFO empty, 0 bytes
10 - DMA FIFO full, 16 bytes
11 - Will not occur
0 - Disable interrupt
1 - Interrupt concurrent
with each DMA burst
of 4 words
0 - Do nothing
1 - Clear DMA buffer
Reset = 0x0000 0xFFC0 4440
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA Master Channel Base Address Low Register (USBD_DMABL)
Low order bits of base address.
USBD_BASE_LO[15:11]
Reset = 0x0000
0xFFC0 4442