Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 11-49
Serial Port Controllers
When the SPORT is enabled to transmit (
TSPEN
set) or receive (
RSPEN
set),
corresponding SPORT configuration register writes are disabled (except
for
SPORTx_RSCLKDIV
,
SPORTx_TSCLKDIV
, and multichannel mode channel
registers).
SPORTx_TX
register writes are always enabled;
SPORTx_RX
is a
read-only register.
After a write to a SPORT register, any changes to the control and mode
bits generally take effect when the SPORT is re-enabled.
Clock and Frame Sync Frequencies
The maximum serial clock frequency (for either an internal source or an
external source) is
SCLK/2
. The frequency of an internally generated clock
is a function of the system clock frequency (as seen at the
SCLK0
or
CLKOUT_SCLK1
pin) and the value of the 16-bit serial clock divide modulus
registers,
SPORTx_TSCLKDIV
and
SPORTx_RSCLKDIV
.
SPxTCLK frequency = (SCLK frequency) / (2

(SPORTx_T 1))
SPxRCLK frequency = (SCLK frequency) / (2

(SPORTx_R 1))
If the value of
SPORTx_TSCLKDIV
or
SPORTx_RSCLKDIV
is changed while the
internal serial clock is enabled, the change in
TCLK
or
RCLK
frequency takes
effect at the start of the rising edge of
TCLK
or
RCLK
that follows the next
leading edge of
TFS
or
RFS
.
The
SPORTx_TFSDIV
and
SPORTx_RFSDIV
registers specify the number of
transmit or receive clock cycles that are counted before generating a
TFS
or
RFS
pulse (when the frame sync is internally generated). This enables a
frame sync to initiate periodic transfers. The counting of serial clock
cycles applies to either internally or externally generated serial clocks.
The formula for the number of cycles between frame sync pulses is:
# of serial clocks between frame sync assertions = 1