Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Load/Store Operation
6-82 ADSP-BF535 Blackfin Processor Hardware Reference
If the branch is taken, then the load is flushed from the pipeline, and any
results that are in the process of being returned can be ignored. Con-
versely, if the branch is not taken, the memory will have returned the
correct value earlier than if the operation were stalled until the branch
condition was resolved.
However, in the case of an I/O device, this could cause an undesirable side
effect for a peripheral that returns sequential data from a FIFO or from a
register that changes value based on the number of reads that are
requested. To avoid this effect, use synchronizing instructions (
CSYNC
or
SSYNC
) to guarantee the correct behavior between read operations.
Store operations never access memory speculatively, because this could
cause modification of a memory value before it is determined whether the
instruction should have executed.
Conditional Load Behavior
The synchronization instructions force all speculative states to be resolved
before a load instruction initiates a memory reference. However, the load
instruction itself may generate more than one memory-read operation,
because it is interruptible. If an interrupt of sufficient priority occurs
between the completion of the synchronization instruction and the com-
pletion of the load instruction, the sequencer cancels the load instruction.
After execution of the interrupt, the interrupted load is re-executed. This
approach minimizes interrupt latency. However, it is possible that a mem-
ory-read cycle was initiated before the load was canceled, and this would
be followed by a second read operation after the load is re-executed. For
most memory accesses, multiple reads of the same memory address have
no side effects. However, for some memory-mapped devices, such as
peripheral data FIFOs, reads are destructive. Each time the device is read,
the FIFO advances, and the data cannot be recovered and re-read.