Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 462 / 1022

SPORT Registers
11-16 ADSP-BF535 Blackfin Processor Hardware Reference
(00=right justify and zero fill unused most significant bits,
01=right justify and sign extend into unused MSBs, 10=compand
using

-law, 11=compand using A-law).
• Endian Format Select.
SPORTx_RX_CONFIG[4]
(
SENDN
). The
DTYPE
,
SENDN
, and
SLEN
bits configure the format of the data words
received over the SPORTs. The
SENDN
bit selects the endian format
(0=serial words are received MSB first, 1=serial words are received
LSB first).
• Serial Word Length Select.
SPORTx_RX_CONFIG[8:5]
(
SLEN
). The
DTYPE
,
SENDN
, and
SLEN
bits configure the format of the data words
received over the SPORTs. The serial word length (the number of
bits in each word received over the SPORTs) is calculated by add-
ing 1 to the value of the
SLEN
field. The
SLEN
field can be set to a
value of 2 to 15; 0 and 1 are illegal values for this field.
• Internal Receive Frame Sync Select.
SPORTx_RX_CONFIG[9]
(
IRFS
).
This bit selects whether the SPORT uses an internal
RFS
(if set) or
an external
RFS
(if cleared).
• Receive Frame Sync Required Select.
SPORTx_RX_CONFIG[10]
(
RFSR
). This bit selects whether the SPORT requires (if set) or does
not require (if cleared) a receive frame sync for every data word.
• Low Receive Frame Sync Select.
SPORTx_RX_CONFIG[12]
(
LRFS
).
This bit selects an active low
RFS
(if set) or active high
RFS
(if
cleared).
• Late Receive Frame Sync.
SPORTx_RX_CONFIG[13]
(
LARFS
). This bit
configures late frame syncs (if set) or early frame syncs (if cleared).
• Clock Drive/Sample Edge Select.
SPORTx_RX_CONFIG[14]
(
CKFE
).
This bit selects which edge of the
RCLK
clock signal the SPORT
uses for sampling data, for sampling externally generated frame
syncs, and for driving internally generated frame syncs. If set, inter-
nally generated frame syncs are driven on the falling edge, and data