Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 333 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 8-1
8 DYNAMIC POWER
MANAGEMENT
This chapter describes the Dynamic Power Management functionality of
the ADSP-BF535 Blackfin processor. This functionality includes:
• Clocking
• Phase Locked Loop (PLL)
• Dynamic Power Management Controller
• Operating Modes
• Voltage Control
Clocking
The input clock into the ADSP-BF535 processor,
CLKIN
, provides the nec-
essary clock frequency, duty cycle, and stability to allow accurate internal
clock multiplication by means of an on-chip, Phase Locked Loop (PLL)
module. In normal operation, the user programs the PLL with a multipli-
cation factor for
CLKIN
. The resulting multiplied signal is the core clock
(
CCLK
). The
CCLK
signal clocks the Blackfin core processor.
A user-programmable value then divides the
CCLK
signal to generate the
system clock (
SCLK
). The
SCLK
signal clocks the Peripheral Access Bus
(PAB), DMA Bus (DAB), External Address Bus (EAB), External Mastered
Bus (EMB) and the External Bus Interface Unit (EBIU). To optimize per-
formance and power dissipation, the ADSP-BF535 processor allows the
core and system clock frequencies to be changed dynamically.