Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-9
Memory
Internal Memory
The ADSP-BF535 processor L1 memory system performance provides
high bandwidth and low latency. Because SRAMs provide deterministic
access time and very high throughput, DSP systems have traditionally
achieved performance improvements by providing fast SRAM on chip.
The ADSP-BF535 processor supports this memory architecture for appli-
cations that require direct control over access time.
The addition of instruction and data caches (SRAMs with cache control
hardware) provides both high performance and a simple programming
model. Caches eliminate the need to explicitly manage data movement
into and out of the L1 memories. Code can be ported to or developed for
the ADSP-BF535 processor quickly without requiring performance opti-
mization for the memory organization.
The ADSP-BF535 processor L1 memory provides:
• A modified Harvard architecture, allowing up to three core mem-
ory accesses per clock cycle (one 64-bit instruction fetch, and two
32-bit data references)
• Simultaneous system DMA and core accesses
• Fast SRAM access for critical processor algorithms and fast context
switching
• Instruction and data cache options for microcontroller code, excel-
lent High-Level Language (HLL) support, and ease of
programming cache control instructions, such as
PREFETCH
and
FLUSH
• Memory protection