Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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General-Purpose Timer Registers
16-4 ADSP-BF535 Blackfin Processor Hardware Reference
Timer Status Registers (TIMERx_STATUS)
Each Timer Status register (
TIMERx_STATUS
) indicates the status of all
three timers and can be used to check the status of all three timers with a
single read. Each
TIMERx_STATUS
register contains timer-enable bits that
enable the corresponding timer (for example,
TIMER0_STATUS
enables
TIMER0). Within a timer’s
TIMERx_STATUS
register, that timer has a pair
of sticky status bits that require a write-1-to-set (
TIMENx
) or
write-1-to-clear (
TIMDISx
) to either enable or disable the timer.
While the timer is enabled, both its
TIMENx
and
TIMDISx
bits read 1. The
timer starts counting three peripheral clock cycles after the
TIMENx
bit is
set. Setting the timer
TIMDISx
bit stops the timer without waiting for any
additional event.
Each
TIMERx_STATUS
register also contains a Timer Interrupt bit (
IRQx
)
and a Timer Overflow bit (
OVF_ERRx
) for each timer. These sticky bits are
set by the timer hardware and may be monitored by software. They need
to be cleared in
TIMERx_STATUS
for each timer explicitly. To clear, write a
1 to the bit.

Interrupt and overflow bits may be cleared at the same time as
timer disable bits.
TIMER1_PERIOD 0xFFC0 2018 Timer1 Period register
TIMER1_WIDTH 0xFFC0 201C Timer1 Width register
TIMER2_COUNTER 0xFFC0 2024 Timer2 Counter register
TIMER2_PERIOD 0xFFC0 2028 Timer2 Period register
TIMER2_WIDTH 0xFFC0 202C Timer2 Width register
Table 16-2. Abbreviated MMR References from Table 16-1 (Cont’d)
Register Name Memory-Mapped
Address Description